This invention relates to semiconductor memory devices and more particularly to a read-only-memory or ROM which is electrically programmable and electrically erasable.
Electrically programmable memory devices of the type shown in U.S. Pat. No. 3,984,822 employs a floating gate in a double level polysilicon MOS ROM structure; for programming, the floating gate is charged by injection of electrons from the channel. Generally, this floating gate EPROM device is erased by exposure to ultraviolet light, requiring an expensive package with a quartz window. Electrically erasable devices of the MNOS type have employed charge storage on a nitride-oxide interface. Electrically alterable ROM's have been developed as set forth in U.S. Pat. Nos. 3,881,180, issued Apr. 19, 1975, and 3,882,469, issued May 6, 1975, and 4,037,242, issued July 19, 1977, all by W. M. Gosney, and my U.S. Pat. No. 4,384,349. Ser. No. 644,982, filed Dec. 29, 1975, all by W. M. Gosney, and my prior application Ser. No. 155,039, filed June 2, 1980, all assigned to Texas Instruments; these devices are floating gate cells with dual injection (both holes and electrons) so that the gates may be charged or discharged by applying suitable voltages. Other electrically alterable EPROM's are disclosed in U.S. Pat. Nos. 4,122,509 and 4,122,544 by Lawrence S. Wall or David J. McElroy, assigned to Texas Instruments. However, the prior cells have exhibited some undesirable characteristics such as large cell size, complex structure, process instability, process incompatible with standard techniques, high voltages needed for programming or erasure, or the like.
It is therefore the principal object of the invention to provide improved electrically erasable semiconductor devices, e.g., electrically alterable, programmable read-only-memory cells. Another object is to provide an electrically erasable memory cell which may be readily formed in a semiconductor integrated circuit, particularly a dual injection type cell. A further object is to provide arrays of electrically erasable memory cells generally compatible with N-channel floating gate EPROM technology.